143 vs 36 minutes is far too big difference
Hardware is just starting to hit it’s stride. This problem will resolve itself within a couple years of new hardware releases and time for people to upgrade
I think a lot of the initial growth of RISCV has been in the embedded space with microcontroller scale chips. Even for Arm it took some time to get to the point they where shipping data center class devices. Arguably personal computing is still lagging for Arm.
RISC-V is not an architecture, it’s an
APIISA.
RISC-V can be built to be energy efficient or fast or cheap top make, just like any other API can have different architectures for those purposes so can RISC-V.
RISC-V can be fast, but it requires massive resources to develop it to be as fast as other leading products.ISA. API exist at a different level. But basically sure. The ISA specifies how instructions should behave. But it’s up to the chip designer to figure out how to accomplish it. Its the difference between HTML and Chrome or Firefox. They both take HTML instructions and use them to present the page as desired. But could get there very differently.
A lot of processor “speed” increase since the 2010s has come from parallelization and SIMD etcetera. Most of the Risc-v cores and SoC to this point have been micro controller or basic proof of concept cores for development. With speeds and performance matching early 2000s systems. But the newer RVA23 systems coming out should mark the start of the more specialized and powerful application processors. But implementation will always play a factor.
it’s up to the chip designer to figure out how to accomplish it
Exactly, which is my point, and since RISC-V doesn’t have a specific chip designer, but the ISA is open, you can’t equal RISC-V ISA in general to any specific chip.
Yes, it would technically be like defining AMD to mean all x86 architecture. Sometimes it would have reflected well. Other times not. But never would have been accurate.
Hopefully though well see smart SIMD subsystems and vector units that can accelerate the operations. Without requiring new hard coded CISC microcode like modern x86. But only time will tell.
This is about what you can get out of RISC-V now, and not the instruction set being “slow”
This maybe true, but it’s also true that are no fast RISC-V devices on the market (even if it is of course possible to develop a fast anything with enough time and resources).
No I repeat RISC-V is an
APIISA, and theAPIISA is by no means inherently slow. There are no fast RISC-V compatible processors, which is a completely different thing.
It’s like claiming the paper in a printer is slow, when obviously it’s not the paper but the printer.If there are no “fast” processors why even bother trying to port a general purpose OS like Fedora to it.
There are no fast processors “yet”
Because it’s an open
APIISA as in actually open, (not bullshit open like OpenAI) and people like that. There are also other factors than speed, like energy consumption, size and price, and of course security, which is becoming a huge issue with traditional products that have back doors.
But for now the major factor is the openness, which means everybody can make one without having to pay license fees to anybody.
